Low-Temperature Atomic-Layer-Deposited High-! Dielectric for p-Channel In0:7Ga0:3As/GaAs0:35Sb0:65 Heterojunction Tunneling Field-Effect Transistor
نویسندگان
چکیده
The interface quality of a low temperature atomic-layer-deposited (ALD) HfO2/Al2O3 bilayer high-! gate dielectric on a GaAs0:35Sb0:65 channel for heterojunction p-channel tunneling FETs is investigated. Lowering the ALD temperature from 250 to 110 !C results in improved capacitance– voltage characteristics and lower interface trap density in metal–oxide–semiconductor capacitor structures. Using the low-temperature ALD high-! dielectric, a GaAs0:35Sb0:65/In0:7Ga0:3As heterojunction p-channel tunneling FET is demonstrated with an improved switching slope and higher on–off current ratio. X-ray photoelectron spectroscopy is performed to investigate the effect of the deposition temperature on the chemical composition of the high-!/GaAs0:35Sb0:65 interface. # 2013 The Japan Society of Applied Physics
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